HiCTL: High Fan-in Differential Capacitive-Threshold-Logic Gate Implementation With an Offset-Compensated Comparator

Computing applications now require highly dense, fast, and complex Boolean computations for bulk bitwise operations. This paper aims to introduce a new threshold logic gate that utilizes a high fan-in with a compact area and low propagation delay. Due to its high fan-in capability and low delay, the threshold logic gate is well-suited for applications demanding fast data-intensive computations. What usually limits fan-in in threshold-logic gates is the offset of the comparator by which the output signal is digitized. The comparator utilized in this work reduces its offset in a very compact area by utilizing a purely capacitive feedback loop. The gate performs sum-of-product and thresholding operations by setting the minimum-sized MOSFET capacitors individually. This is achieved by setting the threshold and input voltages with digital logic levels. The gate operation is dynamic and comprises two phases, in which the inputs and threshold setting are done during the reset phase while the comparator provides the resultant at the evaluation phase. The analysis, properties, and limitations of implementing a high fan-in threshold logic gate are presented by analyzing five gates of fanins 31,63,127,255, and 511, along with a post-layout analysis of the 511 fan-in gate. The gate’s design was validated using 65nm CMOS technology.