Reprogrammable Time-Domain RRAM Based Vector Matrix Multiplier for In-Memory Computing

Architectures utilizing Resistive Random-Access Memory (RRAM) for In-Memory Computing (IMC) have exhibited considerable potential in enhancing the performance metrics of neural networks (NNs). However, IMC configurations that incorporate Vector-Matrix Multipliers (VMMs) necessitate the incorporation of peripheral circuits such as Digital-to-Analog Converters (DAC) and Analog-to-Digital Converters (ADC). This, in turn, results in higher power consumption as compared to RRAM-based circuits. Therefore, we propose a power-efficient RRAM-based Time-Domain VMM (TDVMM). Using Time-Domain implementation, traditional ADC and DAC are replaced with a Digital-to-Time Converter (DTC) and a Time-to-Digital Converter (TDC), thereby conserving substantial hardware resources. The proposed DTC and TDC exhibit power consumptions of $25\mu W$ and $38\mu\mathrm{W}$ and delays of $2\mathrm{~ns}$ and 530ps, respectively. Furthermore, by employing a $4T-1R$ structure with a RESET stop block (RSB), we enable the implementation of a reprogrammable RRAM with four resistive states (2-bit) and a latency of $1.65\mu\mathrm{s}$ and energy/cell of $0.11pJ$, expanding the system’s versatility for diverse applications. The overall energy efficiency of the proposed TDVMM is $217.6\mathrm{GOPS}/\mathrm{W}$, surpassing the SRAM-based TDVMM by a factor of $ 2.33\times$. This higher energy efficiency makes the proposed TDVMM a compelling candidate for IMC applications.