Ultra-Low Voltage Enablement for Standard Cells with Moment based LVF

Rapidly shrinking and increasing on-silicon features associated with growing absolute number of standard cells in SoC and increasing process variability are resulting in need to cover higher sigma to ensure sustainable yield. Thus, digital designs can no longer rely on simple flat margins/derates with OCV (On Chip Variation) based flow to perform signoff. For low power applications, where supply voltage is being scaled (especially when it approaches close to threshold voltage of device) to minimize dynamic and leakage power consumption, the delay values no longer remain Gaussian attributed to large statistical variation. In this paper, we have demonstrated the study of delay variation on several standard cells at lower voltages by comparing reference Spice simulation from Eldo with fast Monte-Carlo (SSD: super saturated design) like approach to generate LVF (liberty variation format) and extending it to moment based LVF. Further, Primetime has been used to analyze cell behavior scalability with reference Spice. Finally, as proof of concept, critical path analysis has been done with Spice as well as Primetime to demonstrate the 95% accuracy achieved in delay scaling at those low voltages.