A 5T Half-SRAM Design for Cold CMOS Physical Unclonable Function Applications and Beyond

With MOSFET characteristics improving dramatically at cryogenic temperatures, a plethora of design opportunities arise. In this paper, we propose a novel $5 T$ Half-SRAM design that exploits cold CMOS operation to offer a versatile solution to SRAM type memories with expanded functionality. The cell latch is not inverter-based and comprises two back-to-back PMOS and NMOS transistors. In cold temperature and low leakage operating regimes, the Half-SRAM array serves as an area efficient and data remanence-aware Physical Unclonable Function with temporal tuning capability. The design eliminates the need for voltage ramp-up and power-on/off cycles and relies on the inherent properties of the Half-SRAM latch. Statistical simulations were performed using TCAD-generated cold CMOS models with varying threshold voltage distributions. The Physical Unclonable Function responses obtained via the experimental simulations were processed using Python. Experiments targeting the cold temperature range [77K-150K] demonstrate 95% reliability for ± 5 % V
DD
fluctuations and response uniqueness $\sim N(50.1 \%, 1.6 \%{}^{2})$.