EDA-ML: Graph Representation Learning Framework for Digital IC Design Automation

The increase in design complexity of very large-scale integrated (VLSI) circuits due to CMOS technology scaling has generated a growing interest in the integration of machine learning (ML) algorithms with traditional electronic design automation (EDA) methodologies. Graph representation learning (GRL) techniques have gained significant attention in recent years owing to the ability to capture complex relationships in graph-structured data. This paper introduces a task-agnostic graph representation learning framework for integrated circuit (IC) design automation, which effectively addresses the challenges presented by diverse data representations and metrics generated during the standard design flow. The framework converts circuit designs and performance metrics extracted from the EDA tools at different design stages into standardized graph representations, capturing structural relationships among design elements and encoding essential characteristics through graph convolutions for meaningful vectorized embeddings. The vectorized embeddings are utilized within a machine-learning flow to predict downstream metrics of an EDA design tool. The effectiveness of the framework is demonstrated by implementing and analyzing two distinct prediction tasks; specifically post-floorplan to post-routing arrival time prediction and post-placement to post-routing interconnect parasitic impedance prediction. The evaluation is performed on a dataset generated from the IWLS’05 benchmark circuits. The analysis of results indicates an improvement in the mean absolute error of 28.71% and an improvement in the mean absolute percentage error of 39.2% for arrival time prediction. For prediction of the parasitic impedance, results indicate an improvement in the mean absolute error of 22.88% and an improvement in the mean absolute percentage error of 19.64%.