Time-Domain-Based Non-volatile In-Memory Computing Architecture Using FeFETs for Binary Neural Network

This paper presents an energy-efficient 128 $\times$ 64 In-Memory Computing (IMC) macro using a novel 5T-2FeFET bit-cell for Binary Neural Networks. This work combines the non-volatile nature of ferroelectric memories and Time-Domain computing topology, which saves energy not only during IMC operations but also during the energy-intensive weight writing process during system bootup from the power-off state. This brief discusses read, write, and IMC operations in the proposed 5T-2FeFET bit-cell, along with an analysis of the designed macro using the proposed bit-cell. The proposed macro supports multiple row activations performing 7936 (128 $\times$ 62) 1b $\times$ 1b multiply and accumulate operations (MAC) in a single clock cycle. MAC output is accumulated as delay on the rising and falling edge of the compute pulse, which is further quantized and converted to the digital domain by a TDC unit giving 1b output. The proposed IMC macro achieves an energy efficiency of 543.6 TOPS/W and throughput of 952.3 GOPS operating at 1 V with a 60 MHz clock frequency.