Implementation of Serial FPDP and 10G Ethernet in an FPGA Based Real Time Embedded Hardware

Today's radar technology demands the use of huge aperture antenna arrays for detection and tracking of targets from a range of hundreds of kilometers. This results in a complex RF manifold where a large number of RF channels in parallel are provided as input to the radar receiver. Subsequently, these inputs are digitized and forwarded to a real time embedded hardware for further processing. Since the number of RF channels are quite high and reception as well as analysis of the incoming data have to be completed for a particular dwell within a matter of few milliseconds, therefore we require high speed serial interfaces from receiver to receive the data and process it in shortest time. Moreover, a copy of the raw data is also required to be forwarded to the signal processor over 10G Ethernet interface. In this paper, we highlight such a design and implementation of a serial Front Panel Data Port (FPDP) interface working at 2.5 Gbaud/lane and a number of such lanes are processed successfully in parallel. Next, we present the design and implementation of the 10G Ethernet interface along with the validation of data integrity at the destination.