Bi-Cubic Interpolation Image Scaling Algorithm Based on FPGA Implementation

Image resizing plays a very important role in image processing, offering good scalability and extensibility. Currently, there are some issues with existing scaling interpolation algorithms, such as complex hardware implementation, high resource consumption, long operation times, and poor realtime performance. To address these challenges, this paper introduces a design method based on the image bicubic interpolation scaling algorithm and optimizes the floating-point operation aspect of image processing. Utilizing the FPGA platform, a step-by-step scaling approach is employed, first performing vertical scaling and then horizontal scaling to achieve parallel processing. This design significantly improves scaling efficiency, and its feasibility is demonstrated through functional simulation.