Efficient Programable Architecture for LWC NIST FIPS Standard ASCON

NIST finalized the LWC standardization process initiated in 2018 by selecting ASCON as the new standard. ASCON is an AEAD cryptography algorithm featuring three variants “ASCON-128, ASCON-128a, ASCON-80pq” vary in terms of input block size and the number of rounds, etc. In this work an efficient programable hardware design that supports all the three AEAD variants is proposed and implemented over GF22nm, SKY130nm ASIC technologies and Spartan-7 FPGA. The programable design is compared to the HW of each individual variant showing the savings in utilizing the programable design which eliminates the need for three separate standalone designs. Results are shown in terms of area, throughput and Energy efficiency. Results show that the programable ASCON saves 61% of total silicon area. The programable HW has an average energy efficiency overhead of 4% compared to dedicated HW design for each variant. In addition to assessing the programmable design, comprehensive study and comparison of the hardware for the individual variants is conducted. ASCON-128a variant is the most energy efficient “2981 Gbits/J” variant with highest throughput “12.16 Mbits/clk”. However, ASCON-128 has the smallest silicon area “2206 μm
²
” on GF22nm.