Architectures and design techniques for real-time image-processing IC's

A set of eight chips that perform real-time image-processing tasks was designed and fabricated with a 4-/spl mu/m NMOS technology. The chips include a 3/spl times/3 linear convolver, a 3/spl times/3 sorting filter, a 7/spl times/7 logical convolver, a contour tracer, a feature extractor, a lookup-table ROM, and two postprocessors for the linear convolver. All chips were designed with architectures that are dedicated to the particular image-processing task to be performed. The image-processing circuits operate on 10-MHz video data (512/spl times/512-pixel images). The design time for the chips was kept to 1.5 man-years by reusing hardware and using (and developing) appropriate CAD tools, ROM generators and a data-path generator were developed to reduce the circuit design time. An image recognition system was built with these custom chips that can recognize two-dimensional objects that are characterized by their closed outer contours. The complete system is controlled by a Sun workstation and operates at rates up to 15 frames/s. The recognition system achieved a 98% recognition rate for eight objects over a wide range of orientation and size variations and a 100% recognition rate without size variations.