A CMOS double-heterodyne FM receiver

Experimental results for a narrow-band, adjustment-free double-heterodyne CMOS FM receiver with a high-Q switched-capacitor IF filter centered at 3 MHz are presented. The integration covers all the filtering and demodulation circuits from radio-frequency circuits (50-100 MHz) to the audio output. An experimental prototype FM receiver exhibiting a 5-mV input sensitivity and a -30-dB quieting level is implemented using 1.75-/spl mu/m double-poly CMOS technology. The chip occupies 7.7 mm and dissipates 80 mW with a 5-V supply.