On‐Chip ESD Protection Circuits – ESD Power Clamps

Summary

This chapter focuses on the classification of the electrostatic discharge (ESD) power clamps, key design parameters, the ESD power clamp design window, trigger elements, clamp devices and issues and problems with ESD power clamps. The ESD power clamp establishes additional current loops within the semiconductor chip to establish alternative current loops for the ESD current flow. With the introduction of the ESD power clamp, the impedance through the current loop can be reduced. Using voltage triggered ESD power clamps, the voltage limitation can be placed on the power supply rail. One of the limitations of breakdown‐triggered networks is that the power supply voltage must reach the breakdown voltage prior to initiating the ESD power clamp. CMOS development utilizes CMOS solutions and simulation, whereas bipolar ESD power clamps can take advantage of bipolar transistor theory. Silicon controlled rectifier networks for usage as ESD power clamps are also discussed.