A 150-ps 9000-gate ECL masterslice

A bipolar masterslice chip with an integration level of 9000 gates is described. Internal gate delays down to 150 ps are achieved by utilizing an advanced processiong technology, OXIS III, and a CML circuit technique with three levels of series gating. The 128 mm/SUP 2/ chip has a typical power dissipation of 20 W. I/O levels at 256 logic pins are standard ECL 100 or 10K.