A Multiplexing/Demultiplexing Transceiver for 565-Mbit/s Fiber-Optic Links

A high-performance silicon bipolar integrated circuit used in a 565-Mbit/s multiplex and optical-fiber transmission system will be described. The paper includes a functional description of the coder/decoder together with details of circuit design and layout techniques used to realize this demanding performance requirement. Measured results are presented which confirm the computer predicted performance. The LSI chip contains over 8000 components with gate delays as low as 250 ps.