3D Stacked DRAM Memories

Summary

This chapter presents the dynamic random‐access memory (DRAM) technology background and the 3D‐DRAM design space. It includes the evolution of DRAM technologies and interfaces and describes the common DRAM architecture and usage. The chapter highlights the large design space and shows an architecture study of a 22 nm 3D‐DRAM. It presents experimental results of additional optimizations using a flexible burst length (BL) and bandwidth (BW) interface. The chapter demonstrates possible optimizations in the 3D‐DRAM and the attached controller using thermal modeling and advanced simulation platforms, such as Gem5 and DRAMSys. It gives a survey across various abstraction levels from circuit‐level to full‐system simulations in the context of 3D‐DRAM explorations and optimizations. The chapter also demonstrates the temperature‐variation‐aware bankwise refresh, which improves the overall refresh rate of the system effectively and decreases the power consumption of 3D‐DRAMs, such as WideIO.