TwinPop: A Resource-Efficient and Highly Linear FPGA-Based Time-to-Digital Converter

The field programmable gate array (FPGA)-based time-to-digital converter (TDC) has been notoriously troubled by its nonlinearity problems. To address it, conventional approaches often demand redundant resources or calibration efforts. In this article, we propose TwinPop to tackle this issue in a resource-efficient manner, by largely reducing chain resources. The key technique is a novel two-phase interpolation process. In the first phase, we alter the logic level of an input signal at programmable intervals and imprint timestamps on signal edges. This can shorten the time intervals to be interpolated in the second phase where a conventional tapped delay line (TDL) is utilized. This means fewer chain resources are needed. In addition, all logic resources can be constrained within a single clock region, significantly mitigating the nonlinearity problem. Finally, the imprinted timestamps are temperature-insensitive, leaving an opportunity to calibrate temperature-induced artifacts in the second phase. We have implemented prototypes using AMD FPGAs. Results demonstrate that our TDC can readily achieve a less than 0.26 least significant bit (LSB) differential nonlinearity (DNL) and 0.42 LSB integral nonlinearity (INL) on AMD 16 nm Ultrascale+ FPGA using only 1/3 chain resources, even without any calibration tricks. With enough redundant resources and statistical calibrations, a 5 ps time resolution can be achieved and 0.2 LSB INL or 0.3 LSB DNL is attainable.