Design of IEC/IEEE 60255-118-1-2018 Compliant SOGI-PLL for Synchrophasor Measurements

A second-order generalized integrator (SOGI) phase-locked loop (PLL) with a linear quadratic regulator (LQR)-based bumpless compensator (BC) switching mechanism is proposed in this article for acquiring synchrophasor measurements compliant with IEC/IEEE 60255-118-1-2018. It has been shown that the SOGI-PLL, without any pre/post-filtering stages, requires two distinct ranges of parameter sets—Set-1 to satisfy steady-state scan, dynamic tests and Set-2 to meet out-of-band (OOB) and harmonic rejection (HR) tests. Therefore, the instance of switching the parameters must be ascertained along with a mechanism to switch between two sets of parameters. Hence, an LQR-based BC switching mechanism is proposed in this article to switch between two parameter sets. The input signal’s unwanted frequency components (harmonic or interharmonic frequency) are quantified using a notch filter and a moving average filter (MAF) to generate the switching signal that activates the transition between the two parameter sets. The performance of SOGI-PLL is tested under steady-state and dynamic test conditions as per IEC/IEEE 60255-118-1-2018 and compared with the enhanced PLL-based approach. The SOGI-PLL performance is found to be better than the enhanced PLL-based approach and is compliant with IEC/IEEE 60255-118-1-2018 under all specified tests. The performance is also tested with an actual voltage signal measured at the laboratory supply, and compliance with the standard was ascertained.