A Fast-Transient Output-Capacitor-Less Low-Dropout Regulator With Direct-Coupled Slew Rate Enhancement

An output capacitorless low-dropout (OCL-LDO) regulator with a direct-coupled slew rate enhancement (DCSRE) technique. This paper proposes a low-dropout regulator with a simple structure, fast transient response, and the ability to reduce overshoot and undershoot, suitable for system-on-chip (SOC) integration. Instead of a high-pass filter, an error amplifier is used to couple the transient signal to achieve better transient response with higher current efficiency and no significant increase in chip area and power consumption, eliminating the tradeoff with the high-pass filter cutoff frequency and simplifying design considerations. Furthermore, the proposed technique would not affect other characteristics of the LDO regulator such as stability, frequency compensation, line regulation, and load regulation. In addition, the analysis is carried out for the case of many poles and zeros in the unity-gain bandwidth (GBW). From the measurement result, the proposed LDO regulator regulated the output voltage at 1 V from the input range 1.8V up to 3.3V, with
$28.8\mu $
A quiescent. The output voltage recovers in
$0.23\mu $
s at a voltage spike of less than 43.5mV, where the load current switches from
$100\mu $
A to 100mA in 100ns. The LDO regulator is fabricated in a
$0.18\mu $
m CMOS process with a core area of 0.0174mm2.