Fractionally-Spaced Equalizers as Clock and Data Recovery Loops

This paper analyzes the phase tracking capability of a fractionally-spaced equalizer (FSE) to propose a dedicated equivalent model as a clock and data recovery (CDR) loop. In contrast to reported FSE studies, our study focuses on quantitative determinations for equivalent CDR loop parameters pertinent to practical CDR designs using FSE. By analyzing second-order statistics and eigenmodes for finite-impulse response (FIR) transversal filter-based FSE as a function of the entire sampling phases, we can estimate the bandwidth tied to the critical eigenmode and additive mean-squared error (MSE). This analysis can guarantee the worst-case behavior of the FSE as a CDR. The behavioral simulation results show the effectiveness of the proposed CDR model by demonstrating the error transfer function, jitter tolerance (JTOL), and bit-error-rate (BER). Based on the analysis, an enhanced decision scheme for the FSE-alternating technique is proposed. The behavioral simulation result shows a 38.5% reduction in the standard deviation of error compared to our previous work for an infinite-range plesiochronous system.