High-Speed High-Density Fault Tolerant Electronics

This paper presents a solution that solves major obstacles in producing fault tolerant ASICs using modern, advanced commercial electronics. Legacy fault tolerant solutions suffer from slow speeds and yield low density electronics, voiding the advantages expected in modern commercial electronics. Systems produced using legacy solutions are greatly inferior in performance to their commercial counterparts, however, commercial electronics are extremely vulnerable to faults such as Single Event Upset (SEU). High Density Self-Restoring Logic (HD-SRL), presented here, provides superior speed and density electronics compared to Triple Modular Redundancy (TMR) and legacy SEU tolerant Dual Interlocked Storage Cell (DICE). In general, HD-SRL achieves density improvements by one process generation over TMR. HD-SRL is applicable to aerospace applications and terrestrial applications such as automotive. The DICE standard storage cell in legacy SEU tolerant designs has a major failure mode for high-speed operation. When an SEU strikes a DICE cell, the cell transitions through a set of intermediate self-recovery states. At high enough circuit speeds, (~150 MHz), the next clock pulse can occur while the DICE cell is in an intermediate state and can easily produce an incorrect output. SEU radiation tolerance historically has been measured in terms of Linear Energy Transfer (LET). NASA specifies electronics with a LET > 38 MeV∙cm
²
/mg as SEU tolerant. The DICE cell demonstrated LET values less than 5 MeV∙cm
²
/mg at speeds above 150 MHz. HD-SRL cells yield an LET > 100 MeV∙cm
²
/mg at process speeds up to I/O pad limits; clearly demonstrating superior SEU tolerance. Based on this data, no one should attempt high speed operation with DICE. Legacy designs and TMR struggle with circuit density. The key design issue is to produce a structure where two or more critical nodes of a critical node set can never be affected by a single SEU. This requirement is met by having critical nodes spaced by at least a defined minimum distance, D
min
. For large feature sized processes such as 250nm, meeting the SEU minimum distance requirement is not a major issue. However, as feature size decreases, the SEU minimum distance requirement can dominate circuit layout. SEU layout constraints in a 22nm circuit layout may resemble constraints found in a 250nm circuit - yielding a significant density penalty. In general, HD-SRL standard cell realizations achieve a one generation improvement over standard TMR approaches. For example, HD-SRL density in a 90nm process is slightly better than TMR density in a 65nm process, HD-SRL density at 65nm is slightly better than TMR density at 45nm, and so on. In full custom layout, the reduction can be larger. This translates into significant cost savings. To illustrate, assume the case with 50 new HD-SRL projects, each requiring 25 wafers are produced utilizing a 40nm process. Density expectations are similar to TMR using a 28nm process, yielding an expected savings of up to $35M. A large automobile application shows a similar savings on the order of $302M.