Gaussian process-based device model toward a unified current model across room to cryogenic temperatures

While the typical temperature range supported by standard MOSFET models is from −55 to 125 °C, recent emerging applications require to operate at a wider temperature range, particularly towards lower temperatures. To address these demands, we apply the sparse Gaussian process to build a unified and compact device model for simulating CMOS circuits operating from room to cryogenic temperatures. Unlike neural networks, the sparse Gaussian process prevents overfitting issues. The evaluation of nMOS and pMOS transistors with various dimensions fabricated using a 65 nm node demonstrates that the I-V characteristics are efficiently and accurately modeled from 4 K to 300 K.