Test Structures of Cross-Domain Interface Circuits with Deep N-Well Layout to Improve CDM ESD Robustness

Charged-device model (CDM) electrostatic discharge (ESD) event is a complex reliability issue for integrated circuits (ICs) in advanced CMOS technology. With the development of ICs toward system-on-chip (SoC) applications, various circuit blocks have been integrated into a single chip. In order to avoid noise coupling between circuit blocks or even to reduce power consumption, the SoC chip was often equipped with separated power domains for different circuit blocks. However, the cross-domain interface circuits between different power domains are particularly susceptible to gate-oxide rupture caused by CDM ESD during cross-domain ESD events. In this study, CDM ESD robustness of cross-domain interface circuits with deep N-well (DNW) was investigated through test structures fabricated in a 0.18-μm CMOS technology.