Functional Design-for-Testability for Functional Test Sequences

Two properties of functional test sequences make them suitable for complementing scan-based tests: they can detect defects whose activation requires large numbers of functional capture cycles while avoiding nonfunctional operation conditions. However, the gate-level fault coverage achievable with functional test sequences is lower than that of scan-based tests. Design-for-testability (DFT) logic that increases the fault coverage creates nonfunctional operation conditions and thus eliminates the advantages of fault detection under functional operation conditions. This article describes a DFT approach that increases the fault coverage of a functional test sequence without creating nonfunctional operation conditions for the fault-free circuit. The key observation underlying this approach is that faulty circuits traverse different states than the fault-free circuit. By activating DFT logic it is possible to maintain the same fault-free state, but change the faulty state in a way that results in the detection of the fault. Experimental results for benchmark circuits demonstrate the extent of the fault coverage increase possible with this approach.