HRM: M-Term Heterogeneous Hybrid Blend Recursive Multiplier for GF(2n) Polynomial

Hardware-efficient polynomial multipliers are desired to satisfy the ever-growing demands of computing within the finite field space toward developing a strong cryptosystems. This research meticulously explores polynomial multiplication from the context of algebraic structures by introducing a novel hetero-blend recursive multiplier that harnesses the strengths of the contemporary state-of-the-art (SOTA) designs. The heterogeneous-blend recursive multiplier (HRM) adeptly merges the footprint efficiency of the Karatsuba multiplier (KM) and the compute-latency benefits of the overlap-free KM (OKM) at higher stages, while at lower bounds, it capitalizes the optimal balance of footprint and compute-latency benefits of the schoolbook multiplier (SBM). To further enhance the performance, HRM integrates the heterogeneous term division throughout its stages which is a characteristic find taken from the prior work on M-term nonhomogeneous Karatsuba multiplier (MNHKA). Furthermore, a MATLAB framework has been devised to expedite the exploration process in the finite field design space resulting from the heterogeneous usage of the M terms across multiple stages. The presented HRM design undergoes comprehensive evaluation when benchmarked against contemporary SOTA designs including KM, OKM, their corresponding homogeneous M term variants referred to as M-term Karatsuba multiplier (MKM), M-term OKM (MOKM) alongside recent variants of composite M-term Karatsuba multipliers (CMKA), MNHKA, and equivalent overlap-free variant M-term nonhomogeneous overlap-free Karatsuba multiplier (MNHOKA). The field-programmable gate array (FPGA) synthesized results for the HRM designs on Zynq ZCU-104 board showcase a best-case of 17.288% lookup table (LUT) savings, 5.68% reduction in delay, and 20.88% gain in area-delay product (ADP) compared with the optimal SOTA design, while also revealing a 13.49% reduction in LUT usage, 5.45% decrease in delay, and 12.97% improvement in ADP when compared with the best among MNHKA and MNHOKA designs. Furthermore HRM designs synthesized on the Cadence GPDK45 library achieved a best-case footprint saving of 16.18%, a critical path delay improvement of 29.53%, a remarkable 45.66% gain in the ADP, a substantial 30.37% reduction in power consumption, and a noteworthy 38.63% improvement in power per area when compared with the optimal SOTA design. In comparison to the leading MNHKA and MNHOKA designs, the HRM designs exhibit a best-case footprint improvement of 5.77%, 8.31% reduction in delay, 16.76% enhancement in ADP, a significant 20.18% power savings, and a notable 17.71% improvement in power-per-unit-area (PPA). To catalyze ongoing research and innovation, hardware designs assessed in this article are made publicly available for further usage.