A Check-and-Balance Scheme in Multiphase Delay-Locked Loop

Multiphase delay-locked loop (MP-DLL) is a technique employed in DDR memory controllers to achieve the required fixed timing delay (tSD) for deskew functionality. Traditionally, the tunable delay line (TDL) that consists of the MP-DLL will surfer the delay period mismatch under the same control code, which is mainly caused by the process variation. In this work, a feature called check and balance (CAB) scheme is developed to fix the delay mismatch among each delay stage, thereby providing a more robust and accurate fixed tSD for double-date-rate (DDR) memory controller with a reasonable amount of area overhead. Compared to the baseline MP-DLL design, MP-DLL with CAB can lower the maximum peak-to-peak (P2P) delay mismatch between delay stages from 51.32 to 6.76 ps at 1.6 GHz, utilizing only a 90-nm CMOS process. This improvement comes with an additional area of 0.0045 mm2 and 0.55-mW power consumption at a 1.0-V supply voltage compared to the baseline MP-DLL.