A 50-Gb/s PAM-4 Receiver With Adaptive Phase-Shifting CDR in 28-nm CMOS

This paper presents a 50-Gb/s receiver (RX) with an adaptive phase-shifting (APS) phase detector (PD) for four-level pulse amplitude modulation (PAM-4) clock and data recovery (CDR). The APS PD adopts a
$\beta $
detector to achieve a unique locking point that resolves the dead-zone problem caused by the combination of the conventional baud-rate PD and adaptive decision feedback equalizer (DFE). The APS CDR is configured with a sign-sign minimum mean squared error (SS-MMSE) PD and an addition of a digital coefficient which is adaptively controlled through the
$\beta $
detector by detecting pre-cursor inter-symbol interference (ISI) dependency of 1-level transitions. Therefore, the proposed CDR does not rely on external coefficients. Furthermore, adaptive programmable gain amplifiers (PGAs) and DFE are implemented with the APS CDR to compensate the pre and post-cursor ISIs, and main-cursor level. Since the adaptive equalizers and the APS CDR share the error samplers, no additional analog hardware is required. Fabricated in 28-nm CMOS technology, a prototype PAM-4 RX operates at 50 Gb/s and occupies an active area of 0.16 mm
$^{2}$
. The RX tested over a 25.3-dB loss channel achieves a bit error rate (BER) of less than 10
$^{-12}$
and energy efficiency of 2.52 pJ/b.