A DOL CMOS static memory cell

A new CMOS static memory cell, called the double-lambda diode (DOL), is described. It offers the speed and the power dissipation advantages of conventional CMOS static memory cells at half the area. The cell uses complementary depletion MOS devices. The processing technology is based on a twin-tub CMOS process. Using 2.5 /spl mu/m design rules the cell area is 500 /spl mu/m/SUP 2/. In addition, a 300 /spl mu/m/SUP 2/ single-lambda diode (SIL) cell using a poly resistor as a load is discussed. Comparisons of these cells with other MOS static memory cells are presented.