Synthesis of Self-Timed Circuits with Memory

Self-timed (ST) circuits have a number of advantages over synchronous counterparts. They utilize natural interaction between digital units based on data availability. Combinational ST circuits use redundant coding of information and a two-phase operating discipline, which makes it possible to detect the successful circuit switching completion in each phase. The combinational ST circuit synthesis has been well studied, formalized, and implemented in several existing computer-aided design systems for asynchronous digital units. It is based on dualizing the logical function system in order to convert single information signals into dual-rail signals with a null or unit spacer and supplementing an additional indication subcircuit that detects the completion of ST circuit switching into the current phase. The synthesis of ST circuits with memory is less amenable to formalization. The paper considers the problem of implementing typical ST units with memory, namely latches and flip-flops. It analyzes ST latch and flip-flop implementation features and their interaction with the combinational environment, which requires dual-rail coding of information signals, and offers effective circuit solutions that ensure the adequacy of their behavior in relation to synchronous counterparts.