Design and Implementation of High-Performance Multi-Level Approximate Multiplier

In computers and digital electronics, digital multiplication is a fundamental mathematical operation. Because multiplier applications are inherently error-tolerant, approximate multipliers are created. Approximate multipliers are primarily designed to accomplish a compromise between precision and enhanced performance factors like speed, power efficiency, and efficient use of chip area in digital circuit designs. They aim to deliver results that closely approximate the exact multiplication outcome while bringing significant benefits to a wide range of applications. In this study, we present a novel 4-2 approximation compressor architecture that makes use of multiplexers. This is achieved by replacing portions of the normal AND/OR gates with approximate MUX-based logic. The various high-speed 5-3, 10-4, 15-4, and 20-5 compressors are being developed using MUX-based logic. Utilizing the 5-3,10-4, 15-4, and 20-5 compressor structures, the multiplier's partial products are combined. The circuits under investigation are used to create
$8 \times 8$
multipliers,
$16 \times 16$
multipliers,
$32 \times 32$
multipliers, and
$64 \times 64$
multipliers implemented in CMOS 45nm technology. The suggested compressor achieves an 11.9% reduction in delay when compared to the precise compressor and the suggested multiplier achieves a 39% reduction in delay Consequently, this design is well-suited for applications demanding increased processing speed.