Analysis of Operational Amplifier Topologies for a Low Power Analog to Digital Converter

Innovations in circuit design techniques have made the comparator circuits, amplifier circuits, data converter circuits, mixer circuits, high efficient current regulators, phase locked loops etc. to operate at high speeds, less silicon area and reduced power consumption. Besides this hand held devices are becoming an important part of everybody's life style. One of the important and necessary circuits in these devices is operational amplifiers implemented using complementary metal oxide semiconductor technologies. With the voltage scaling possible through metal oxide semiconductor integrated circuits, the circuit operating speed, power consumption and area can be scaled further down. The techniques substrate bias control and VDD control are used in this work. In this paper, design is carried out for two-stage operational amplifier in both 0.09micrometer and 0.18 micrometer process technology. Important specifications linked to 2-stage operational amplifier such as figure of merit, power consumption, slew rate, gain and phase margins, CMRR and output voltage swings are calculated and compared in both the process technologies. The entire simulation is carried out at a circuit voltage of 1.8V. Simulation results reveal a significant enhancement in the numerical values of phase margin, slew rate, figure of merit and common mode rejection ratio values.