3D Stacking of RAM–Processor Chips Using TSV

Summary

3D chip stacking using through‐silicon vias (TSVs) can provide smaller footprints, higher performance, lower power, and higher reliability without shrinking the chip or integrating differing technologies on the same chip. TSVs are vertical holes in the chip that are filled with a conducting metal usually copper. 2D chips with embedded memory integrated with logic have developed some of the same issues from long interconnects and wide memory buses that systems previously had, such as coupling noise and ground bounce. A well‐designed 3D stacking configuration of memory and processor using TSVs can significantly shorten on‐chip buses. Early 2.5D configurations have used passive interposers with chips side by side on the interposer to connect chips. Another early configuration is a stack of identical DRAM chips connected with TSVs called a memory cube. Standards for chips reconfigured for 3D TSV packaging have been posted and new standards are being discussed. In the future, new design tools optimized for 3D can repartition chips and systems in 3D to optimize these benefits. Challenges of 3D stacking using TSVs include instability, heat dissipation, mechanical stress, and thermal stress. Remote connections between processor and memory chips are also possible and examples of work in inductive coupling or processor and memory are discussed. In the future, optical interconnects are also possible.