A pair of bipolar memory LSI chips for mainframe computers

A pair of bipolar memory chips has been developed. One is an LSI consisting of a 3072 bit RAM and 470 logic gates on the same chip. It has a typical address access time of 6.7 ns and a typical power dissipation of 3.9 W. It is used in the translation lookaside buffer and the buffer address array of Hitachi's M200H computer to speed up dynamic address translation and buffer storage control. The other chip is a standard 1K bit RAM with a typical address access time of 5.5 ns and a typical power dissipation of 800 mW. It is used in the buffer storage. The primary fabrication process employs oxide isolation with double layer metallization, with minimum line width-plus-spacing of 8 /spl mu/m.