Low-Power 8x8 S-RAM Memory Design: CADENCE-Based Simulation and Analysis

Static random access memory (SRAM) and dynamic random access memory (DRAM) are two types of memory circuits that are important for system architecture and are related to power consumption. Memory usage can be reduced, thus improving reliability, performance and overall cost. Low-power SRAM is becoming increasingly important in many VLSI chips. Therefore, it is important to have a lower power SRAM that operates at a higher speed. The aim of this project is to design and simulate an 8x8 low-power SRAM memory array using Cadence tools. Initially, different topologies of SRAMs such as 6T, 7T, 8T and 9T were designed and analyzed in read and write mode. To build an SRAM memory array, different modules such as decoders, logic amplifiers, SRAM arrays, and multiplexers need to be designed and integrated. The performance of SRAM topologies was compared taking into account parameters such as propagation delay, static power consumption, static noise and corner analysis. The topology with the best performance is then considered for the low power implementation using Sleep technique.