Design of Low Power Ternary Inverter with Line Tunneling based Silicon Nanotube Tunnel FETs

In this article, we propose a standard ternary inverter (STI) with novel line tunneling based Gate overlapped Source Nanotube Tunnel FETs (GoS-NT-TFETs) without any additional components. Using calibrated 3D simulations, we demonstrate that with appropriate gate metal work-function (i) gate bias independent drain to channel tunneling and (ii) gate bias dependent within source line tunneling take place. The first tunneling mechanism results in third output state and second tunneling mechanism results in binary output state in the Voltage Transfer Characteristics (VTC). The ternary inverter designed using the proposed device exhibits lower static and dynamic power dissipation at $\mathrm{V}_{\mathrm{DD}}=0.5 \mathrm{~V}$ in comparison to conventional T-CMOS inverter.