Single Event Transient Effects in Raised Source/Drain Double-Gate 1-T DRAM

Single event transient (SET) due to heavy ion strike is a major reliability concern in digital VLSI circuits. In this paper, the SET effects in a capacitorless 1-T DRAM with raised source/drain double-gate MOSFET are analyzed. The ion strike is considered in 1-T DRAM during hold/read ‘0’ operation since the effect is more prevalent during this period of operation. The retention time and sense margin decreases for higher back gate bias and linear energy transfer.