Enhancing Performance of SiGe/InAs Junctionless TFET

This article investigates how to optimize device performance by strategically utilizing semiconductor energy levels and gate dielectric properties. The primary objective is to optimize Silicon-Germanium (SiGe) / Indium Arsenide (InAs) Junctionless Tunnel Field-Effect Transistors (TFETs) by strategically improving their functionality. The process intends to optimize the design of junctionless TFETs for improved functionality, as they represent promising candidates for the next generation of low- power electronic devices. In the pursuit of controlling tunneling properties, the structure initiates a comprehensive investigation into band gap engineering within the SiGe channel. The optimized device’s on-state current while maintaining the desired subthreshold swing characteristics through meticulous adjustments to the band gap profile. The analysis strikes a balance between tunneling efficiency and gate control over the channel by carefully selecting and fine-tuning the gate dielectric properties.