Quantum Confinement Imposed Constraints in ULP Circuits with Junctionless FET

The interplay between quantum confinement (QC) and parameter variations in ultralow power (ULP) inverter and Schmitt trigger (ST) with nanowire junctionless transistor is evaluated. Process variations under QC lead to enhanced threshold voltage $(V_{\mathrm{T}\mathrm{H}})$ variability which degrades noise margin of ULP inverter. Similarly, QC induced higher VTH variation in n- or p-subcircuit degrades hysteresis width of ULP ST. Process variations under QC need to be carefully analyzed for optimum performance for ULP applications.