Benchmarking IWO-based Logic Circuits for Monolithic 3D Integration

This study shows a comprehensive evaluation of Back End Of Line (BEOL) compatible Tungsten doped amorphous Indium Oxide (a-IWO) Dual-Gate (DG) Thin Film Transistor (TFT) showcasing high performance at an ultra-thin channel thickness of 7 nm with on-off current ratio $\sim 4\times 10^{9}$. In this study, digital logic gates such as the inverter, NAND, and NOR gates were tested against 28 nm FDSOI CMOS technology. The results showed that the TFT technology outperformed the FDSOI technology in terms of static and dynamic power consumption, as well as energy efficiency. The improvements reported by TFT were quite significant. For the NAND logic implementations, the performance improved by factors of $1.53\times, 10.3\times$, and $6.4\times$, respectively. However, for the NOR logic implementation, the performance improvement factors were $0.33\times, 14.8\times$, and $8.8\times$, respectively.