Analytical Model for Parasitic Resistance of N-stack Forksheet FETs Using Modified Transmission Line Method

Although Forksheet FETs with high electrostatic integrity and optimized standard cell height have been proposed for the sub-5 nm technology node, the incessant scaling of the gate length and source/drain contact area has resulted in a significantly high source/drain (S/D) series resistance and a considerably reduced channel resistance. The high source/drain series resistance tends to dominate at high bias voltages limiting the drive current. Therefore, it becomes essential to develop an analytical model for design optimization of different parasitic resistance components of Forksheet FETs. To this end, in this work, for the first time, we have formulated analytical model for the parasitic source/drain resistance $\mathrm{R}_{\mathrm{sd}}$ for the N-stack FSFETs using a modified transmission line model which captures the non-uniform current density within the source/drain extension regions. Furthermore, the developed model shows good agreement with the calibrated TCAD simulations even for extreme cases of geometric parameter variation.