Unveiling the Role of Interface and Dielectric Wall Traps with Self-heating Induced Aging Prediction of Forksheet FET

Evaluating different variability merits is a crucial research step to look after the reliability and aging of the device. Generally, the self-healing effect (SHE) is a prime factor in scaled geometrical devices. In this paper, we performed a SHE-induced performance investigation of the vertically stacked Forksheet (FS) FET. Using well-calibrated TCAD setup, we analyzed: (i) impact of SHE-induced performance degradation on nFET/pFET (self-side) and either side of the dielectric wall (a separating wall between nFET & pFET); (ii) the significance of concentration and location of the trap charges present at Si-SiO
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and sheet-dielectric wall (DW) interface; (iii) the impact of ambient temperature on FSFET; (iv) the prediction of early aging using a well-defined merit of threshold voltage $\left(\mathrm{V}_{\text {th }}\right)$ shift by ±50 mV. Thus, the proposed investigation is worth acquiring the design guideline of a reliable Forksheet FET.