Exploiting Single Ferroelectric FET for Efficient Implementation of Majority Gate Function for Approximate Computing

Approximate computing is an emerging paradigm that exhibits a significantly high area- and energy-efficiency by relaxing the constraint on computational accuracy. The majority-gate function forms the fundamental block of the approximate adders and multipliers. In this work, for the first time, we propose a novel implementation of a three-input majority gate function utilizing a single ferroelectric FET (FeFET). Furthermore, we propose a novel input-to-voltage mapping scheme and exploit the drain-erase phenomenon to implement the majority-logic functionality in a single FeFET. For a proof-of-concept demonstration, we have utilized an in-house developed experimentally calibrated SPICE-compatible model for Fe-FETs, and our results indicate that the proposed implementation performs the majority logic function efficiently while consuming an average read energy of 0.577 pJ. The proposed implementation may pave the way for the realization of compact and energy-efficient multi-bit adders and multipliers for approximate computing applications such as image processing, data analysis, etc.