Experimental Studies of Extended Drain MOSFET in 130-nm SOI Technology for Power Amplifier Design

The increased demand for high-speed wireless communication has resulted in integrating many wireless technologies into a single silicon chip. In this context, power amplifiers (PAs) are crucial in ensuring efficient signal transmission. This paper presents the small signal and large signal measurements of common source (CS) and cascode power cells for sub6 GHz. The power cells are fabricated in Globalfoundries 130-nm SOI technology using thick oxide ednfet and thin oxide devices. A comprehensive study was performed for CS power cell with device width scaling, length scaling and frequency scaling. The power cell, presented in this work takes advantage of improved CMOS process technology to produce a small footprint while providing high output power and efficiency. Measurement results on a 4mm CS power cell showing small signal gain of 18.54dB/12.63dB and Output power of 28.58dBm/28.25dBm with PAE of 51.5%/53.3% at 2. 4GHz/5.8GHz in 3dB gain compression points (Psat). The measured cascode device at 2. 4GHz/5.8GHz achieves a higher gain of 33. 9dB/24.8dB and 23.1dBm/22.7dBm of output power with 61.6%/57.5% PAE at Psat point.