An Efficient 1.4-GS/s 10-bit Timing-Skew-Free Time-Interleaved SAR ADC With a Centralized Sampling Frontend

This article presents a timing-skew-free time-interleaved (TI) successive-approximation register (SAR) analog-to-digital converter (ADC). By implementing an architecture with a single sample-and-hold (S/H) network, this design eliminates the need for a costly timing-skew calibration. Additionally, compared to architectures that utilize multiple S/H networks, it offers hardware and power savings. As a result, the proposed design is efficient in terms of energy and area, making it suitable for applications that require multiple ADC channels. A prototype ADC is designed and fabricated in a 28-nm CMOS process. The TI SAR ADC, running at 1.4 GS/s, achieves a signal-to-noise-and-distortion ratio (SNDR) and spurious free dynamic range (SFDR) of 48.1 and 58.4 dB with a Nyquist input, respectively. It dissipates 24 mW, leading to a Walden figure-of-merit (FoM) of 82.4 fJ/conv.-step. The chip occupies an active area of 0.06 mm2.