A1RL: Approximate 1-Row-LUT-Based Low-Power Signed Multipliers for DSP and Machine Learning Applications on FPGAs

Approximate multipliers are promising circuits to meet the demands of energy constrained hardware accelerators of Digital Signal processing (DSP) and Machine learning applications. Field programmable gate arrays (FPGA) are imperative for these applications due to their reconfigurability and inherent parallelism. Conventional multipliers use multiple Look-up-table (LUT) rows for designing approximate multipliers. For the first time, in this paper, approximate Booth multipliers are build using a single row of LUTs called the Approximate 1-row-LUT-based multipliers (A1RL). The multipliers are realized using approximate Karnaugh maps (Kmaps) for the sum of partial products. The proposed multipliers provide a reduction of 16.66-33.33%, 5.23-26.68% and 28.99-78.85% in Area(LUT), Critical path delay (CPD) and power delay product (PDP), respectively.