Programmable Binary Weighted Time-Domain Vector Matrix Multiplier for In-Memory Computing

In-Memory Computing (IMC) architectures employing non-volatile memories (NMVs), such as RRAM, have shown considerable promise in improving the performance of artificial neural networks (ANNs) in terms of power and energy consumption. The Vector-Matrix Multipliers (VMM) used in IMC architectures require many peripheral circuits, such as Digital-to-Analog Converters (DAC) and Analog-to-Digital Converters (ADC), consuming more power than RRAM-based circuits. An increase in the VMM size increases the area and power of the peripheral circuits. Hence, RRAM-based power optimal peripheral circuits are imperative for efficiently realizing of IMC architectures. Replacing ADC and DAC with time domain circuits, Digital-to-Time Converter (DTC) and Time-to-Digital Converter (TDC) can reduce the power consumption of the peripheral circuits. However, the contemporary DTCs and TDCs implemented digitally consume more area and power. This paper proposes a DTC and a TDC for RRAM-based time domain vector-matrix multiplication (TDVMM). The proposed DTC and TDC consume
$25\ \mu W$
and
$31.5\ \mu W$
power exhibiting
$2\ ns$
and 430 ps delay, respectively. The DTC and TDC are realized with 87.4% and 76.6% fewer components than the contemporary DTCs and TDCs. Further, for the first time, the
$4T-1R$
structure adapted for realizing SET and RESET enables the reprogramming of cells in RRAM-based TDVMM. The overall energy efficiency of the proposed TDVMM is 169.4
$GOPS/W$
, which is
$1.82\times$
more than the SRAM-based TDVMM, making it a suitable candidate for In-Memory computing applications.