Harnessing Hybrid Clock Tree Topology to Boost PPA in Highly Utilized Designs

The relentless miniaturization of process technology has led to exceptionally dense designs, thereby presenting a myriad of challenges for chip designers who strive to achieve targeted power, performance, and area benchmarks. Within these densely populated designs, the clock tree synthesis assumes an imperative role, profoundly influencing timing convergence and power expenditure. Traditional clock tree synthesis is limited by uncontrolled clock depth leading to higher latency and skew values. The shortcomings of traditional clock strategies are driving engineers to seek innovative methods for boosting the Power, Performance and Area (PPA). This paper presents a Hybrid Clock Tree Topology (HCT) as an integrated approach to address clocking, timing convergence and frequency targets in highly utilized designs. The proposed HCT topology is an automated solution that efficiently allocates tap points to address clock tree optimization and leverages beneficial skew management. Our experimental analysis of several highly utilized and highly congested designs operating around 1.2GHz indicate the benefits of this technique. The results exhibit significant improvements, such as 36.98% reduction in insertion delay, 38.88% decrease in global skew, 16.07% reduction in total power, 14.15% reduction in clock power, and 12.96% saving in routing resources. The proposed topology offers notable enhancements in power, performance, and area targets, providing an effective way forward for future chip design.