Efficient Hardware Design of Parameterized Posit Multiplier and Posit Adder

Posit arithmetic, an alternative to IEEE 754 f1oating-point arithmetic, offers higher precision and a wider dynamic range. In posit, the number of bits allocated to fractional part varies based on the magnitude of the number. For representing very large/small numbers, the exponent field uses more bits and fractional field uses less bits. The run-time variations in posit number fields inherit an interesting hardware design challenge for posit arithmetic architectures. The word size (N) and exponent size (es) defines posit format. For the same word size, it is possible to have different dynamic range and accuracy based on exponent size (es) which is absent in floating-point. This work proposes optimized parameterized hardware implementation of posit operators, namely multiplier and adder along with its pipelined architectures in Verilog HDL. Implementation results on Virtex-7 (xc7vx330t-3ffgI157) FPGA for posit multiplier and posit adder are found to be better than the existing designs. Non-pipelined posit multiplier's datapath delay reduced by 21 % and the number of LUTs are reduced by 9%. Non-pipelined posit adder's datapath delay reduced by 4 % and the number of L UTs are reduced by 15 %. Software implementation of the posit operators in MATLAB is carried out for validation. There is a 100% match between software and hardware results.