A Transient-Enhanced Capacitor-Less LDO With 30-MHz Bandwidth and High Slew Rate

This paper introduces a novel multi-loop capacitor-less low dropout regulator (CL-LDO) that achieves enhanced transient response and superior load regulation. The proposed CL-LDO incorporates a fast feedback loop (FFL) based on a bandpass filter, extending the bandwidth and reducing response time. High gain and high slew rate (SR) class AB amplifiers are utilized in the main feedback loop (MFL) to improve accuracy, load regulation, and transient response at low frequencies. Benefitting from the usage of the class AB amplifier, the LDO achieves improved positive and negative SR. Moreover, the impact of systemic offset voltage is eliminated to attain better load regulation. Furthermore, the auxiliary fast feedback loop consisting of a voltage spike detection and elimination circuit enhances transient response at high frequencies. The CL-LDO is implemented using a CMOS 0.18 μm process with 1.8 V
$V_{IN}$
and 1.5 V output voltage. Simulation results demonstrate reduced overshoot (18 m V) and undershoot (55 m V) with a maximum setting time of 210 ns for a transient time edge of 100 ns, ranging from 1 mA to 30 mA. Additionally, the proposed LDO achieves a load regulation of 0.05
$\mu \mathrm{V}/\text{mA}$
, Overall, the presented CL-LDO design showcases improved transient response, load regulation, and accuracy, making it highly suitable for edge system-on-chip (SOC) applications.