CAWPR: Contention Aware Write Preemptive Management Policy for Hybrid Last Level Caches

Spin Transfer Torque Magnetic Random Access Memory (STT-MRAM) based last-level caches (LLC), are promising candidate for implementing various network-on-chip (NoC) applications due to their high density, non-volatility, low operating conditions, high endurance and negligible leakage current. Although, the STT-MRAM speeds have reached the state-of-the-art SRAM designs, STT-MRAM still has some challenges that it needs to overcome before it can be used as a substitute for on-chip LLC. In this paper, we present a programming methodology called Contention Aware Write PReemptive management policy or CAWPR, to optimize the energy performance of STT-MRAM based LLC. We also modify the existing Gem5 tool, to handle simultaneous cache requests, to report correct application execution times and then apply CAWPR to handle critical and non-critical requests encountered by the STT-MRAM based LLC. It is observed that for a system with balanced critical and non-critical write requests, system performance using CAWPR improved by ~33% while maintaining the system performance.