Ternary Systolic Array Architecture for Matrix Multiplication in CNFET-Memristor Technology

This paper presents ternary systolic array archi-tecture for matrix multiplication for ternary neural networks and image processing algorithms in ternary logic. As part of the architecture, we have proposed a processing element of a systolic array architecture. The processing element is designed using a partial product calculator, which does the multiply-accumulate operation using single-digit multipliers and adders. All proposed circuits are designed in CNFET-Memristor technology and sim-ulated using Cadence Virtuoso. The propagation delay, power, and power delay product of the proposed circuits are calculated using simulations. The proposed matrix multiplication is used in the Gaussian smoothing of images and results were presented.